Design of Deep Learning Technique Based Side Channel Attack Analysis for System on Chips
Ahmed Imran Fattah
Department of Computer Techniques Engineering, Al-Kadhum College (IKC), Baghdad, Iraq
Mohammed Saeb Nahi
Department of Computer Techniques Engineering, Al-Kadhum College (IKC), Baghdad, Iraq
Hassan Jameel Mutashar
Department of Computer Techniques Engineering, Al-Kadhum College (IKC), Baghdad, Iraq
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http://doi.org/10.37648/ijps.v17i01.006
Abstract
The effectiveness of deep learning techniques has increased in recent years, making it possible to assess side channel attacks on System-on-Chips (SoCs). Specifically, this is due to the fact that they provide a sophisticated method to capitalise on the unintended loss of information that occurs during cryptographic procedures. And couch durable seating solution that adapts to your lifestyle and design preferences. In this particular scenario, it is very necessary to collect information on side channels, such as power consumption or electromagnetic emissions. There is a procedure called as preprocessing that involves cleaning and modifying the raw data in order to make it more acceptable for input into neural networks. The orologi replica specifics of the side channel information are what define whether or not a deep learning architecture, such as Recurrent Neural Networks (RNNs), Long Short-Term Memory (LSTM) networks, or other specialist structures, should be used. Following this, the architecture of the model is painstakingly created, consisting of layers, units, and activation functions, with the purpose of effectively collecting and deciphering the intricate patterns that are associated with the processing of sensitive data on the SOC.
Keywords:
Deep Learning; Side Channel Analysis; Attacks; System on Chip and AES
References
- A. A. Ahmed, M. K. Hasan, et. al., 'Design of Lightweight Cryptography based Deep Learning Model for Side Channel Attacks,' 33rd International Telecommunication Networks and Applications Conf., Australia, 2023, p. p. 0325 - 0328, https://doi.org/10.1109/ITNAC59571.2023.10368560
- F. Kenarangi et. al., 'Security Network On-Chip for Mitigating Side-Channel Attacks,' ACM/IEEE SLIP, USA, 2019, p. p. 01 - 06, https://doi.org/10.1109/SLIP.2019.8771328
- A. A. Ahmed, M. K. Hasan, et. al., 'Optimization Technique for Deep Learning Methodology on Power Side Channel Attacks,' 33rd International Telecommunication Networks and Applications Conf., Melbourne, 2023, p. p. 080 - 083, https://doi.org/10.1109/ITNAC59571.2023.10368481
- Méndez Real, Maria, et. al., 'Physical Side-Channel Attacks on Embedded Neural Networks: A Survey' Applied Sciences 011, no. 015:6790. https://doi.org/10.3390/app11156790
- A. A. Ahmed et al., 'Detection of Crucial Power Side Channel Data Leakage in Neural Networks,' 33rd International Telecommunication Networks and Applications Conf., Melbourne, 2023, p. p. 057 - 062, https://doi.org/10.1109/ITNAC59571.2023.10368563
- Ruize Wang, et. al., “Far Field EM Side-Channel Attack on AES Using Deep Learning”, In Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security, USA, 2020, 035–044, https://doi.org/10.1145/3411504.3421214
- A. A. Ahmed and M. K. Hasan, 'Design and Implementation of Side Channel Attack Based on Deep Learning LSTM,' IEEE Symposium TENSYMP, Australia, 2023, p. p. 01 - 06, https://doi.org/10.1109/TENSYMP55890.2023.10223652
- Song, Shijie, et. al., 'Overview of side channel cipher analysis based on deep learning.' Journal of Physics: Conf. Series. Vol. 01213. No. 02. IOP, 2019. Https://doi.org/10.1088/1742-6596/1213/2/022013
- Ahmed, A. A., Hasan, M. K., et. al., “Deep Learning Method for Power Side-Channel Analysis on Chip Leakages”, Elektronika Ir Elektrotechnika, 29(6), 50 - 57. https://doi.org/10.5755/j02.eie.34650
- Prouff, E., et. al., “A Comprehensive Study of Deep Learning for Side-Channel Analysis”, IACR Transactions on Cryptographic Hardware and Embedded Systems, 2020, 0348 – 0375.
- Ahmed, A. A., Hasan, M. K., Islam, et. al., “Design of Convolutional Neural Networks Architecture for Non-Profiled Side-Channel Attack Detection”, Elektronika Ir Elektrotechnika, 29(4), 2023, 076 - 081. https://doi.org/10.5755/j02.eie.33995
- B. Hettwer, D. Fennes, et. al., 'Deep Learning Multi - Channel Fusion Attack Against Side-Channel Protected Hardware,' 57th ACM/IEEE, DAC, USA, 2020, p. p. 01 - 06, https://doi.org/10.1109/DAC18072.2020.9218705
- S. Picek, Guilherme, et. al., “SoK: Deep Learning-based Physical Side-channel Analysis”. ACM Computer Survey, 55, 11, Art. 227, 2023, 35. https://doi.org/10.1145/3569577
- Kubota, Takaya, et al. 'Deep learning side-channel attack against hardware implementations of AES.' Microprocessors and Microsystems, 87 (2021): 103383, https://doi.org/10.1016/j.micpro.2020.103383
- A. Golder, D. Das, et. al., 'Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 027, no. 012, p. p. 02720 - 02733, Dec. 2019, https://doi.org/10.1109/TVLSI.2019.2926324
- Do, N.-T., et al. “On the performance of non-profiled side channel attacks based on deep learning techniques”, IET Inf. Secur. 17(3), 0377–0393, 2023. https://doi.org/10.1049/ise2.12102
- P. Kashyap, F. Aydin, et. al., '2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning,' in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 6, p. p. 1217 - 1229, 2021, https://doi.org/10.1109/TCAD.2020.3038701
- Josef Danial, Debayan Das, et. al., “EM-X-DL: Efficient Cross-device Deep Learning Side-channel Attack With Noisy EM Signatures”, J. Emerg. Technol. Comput. Syst. 018, 01, Article 04, 2022, 017 pages. https://doi.org/10.1145/3465380
- Timon, B. “Non-Profiled Deep Learning-based Side-Channel attacks with Sensitivity Analysis”. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019(2), 0107–0131. https://doi.org/10.13154/tches.v2019.i2.107 - 131
- Van der Valk et. al., 'Deep Learning Side-Channel Attack Resilient AES-256 using Current Domain Signature Attenuation in 65nm CMOS,' IEEE CICC, USA, p. p. 01 - 04, 2020, https://doi.org/10.1109/CICC48029.2020.9075889.
